The processes used to manufacture modern integrated circuits often involve precise alignment to ensure that newly formed features are correctly positioned relative to previously formed features. The accuracy of this alignment may depend on the sometimes imprecise operation of manufacturing tools, such as photolithography steppers, and on other manufacturing conditions with potential for variability. In practice, if a photolithography tool fails to achieve an alignment within an acceptable tolerance, or if some other alignment error occurs in an in-process integrated circuit, it is useful to detect this error as quickly as possible. For example, in the context of a photolithography process in which a layer of photoresist is exposed to light to form a pattern for subsequently deposited material, if an error in the alignment of this pattern is detected before subsequent processing, the patterned photoresist can often be removed and the photolithography process repeated to correct the error. If the error is not detected, the placement of the subsequently deposited material will likely be incorrect and the wafer carrying the in-process integrated circuit may need to be scrapped as a result.
Overlay metrology can be used to ensure accurate alignment of features as integrated circuits are manufactured. In a conventional approach to overlay metrology, alignment elements are formed at overlapping levels of an integrated circuit by photolithography along with features of electrical components of the integrated circuit. The positions of the alignment features are detected by a microscope and compared from one level to another. A vector difference in the position of a given alignment element at one level and a counterpart alignment element at another level can be used to determine an overlay offset between the levels. If an overlay offset measured in this manner is too high, an alignment error has likely occurred. The source of the error can then be identified and corrected, and the affected wafer, batch of wafers, production run, etc. can be reworked as needed. As integrated circuits have become increasingly dense, alignment tolerances have become tighter and alignment errors have become more difficult to avoid. Accordingly, liberal use of overlay metrology is often warranted in conjunction with processes used to manufacture modern integrated circuits. With this in mind, there is a continuing need for improvement in the field of overlay metrology.